LVD1EN=0, BUSMEN=0, RPEEN=0, IWDTEN=0, LVD2EN=0, SPEEN=0, RECCEN=0, WDTEN=0, NMIEN=0, BUSSEN=0, OSTEN=0
Non-Maskable Interrupt Enable Register
| IWDTEN | IWDT Underflow/Refresh Error Interrupt Enable 0 (0): IWDT underflow/refresh error interrupt is disabled. 1 (1): IWDT underflow/refresh error interrupt is enabled. |
| WDTEN | WDT Underflow/Refresh Error Interrupt Enable 0 (0): WDT underflow/refresh error interrupt is disabled. 1 (1): WDT underflow/refresh error interrupt is enabled. |
| LVD1EN | Voltage-Monitoring 1 Interrupt Enable 0 (0): Voltage-monitoring 1 interrupt is disabled. 1 (1): Voltage-monitoring 1 interrupt is enabled. |
| LVD2EN | Voltage-Monitoring 2 Interrupt Enable 0 (0): Voltage-monitoring 2 interrupt is disabled. 1 (1): Voltage-monitoring 2 interrupt is enabled. |
| Reserved | These bits are read as 00. The write value should be 00. |
| OSTEN | Oscillation Stop Detection Interrupt Enable 0 (0): Main Oscillation stop detection interrupt is disabled. 1 (1): Main Oscillation stop detection interrupt is enabled. |
| NMIEN | NMI Pin Interrupt Enable 0 (0): NMI pin interrupt is disabled. 1 (1): NMI pin interrupt is enabled. |
| RPEEN | RAM Parity Error Interrupt Enable 0 (0): SRAM Parity Error interrupt is disabled. 1 (1): SRAM Parity Error interrupt is enabled. |
| RECCEN | SRAM ECC Error Interrupt Enable 0 (0): SRAM ECC Error interrupt is disabled. 1 (1): SRAM ECC Error interrupt is enabled. |
| BUSSEN | MPU Bus Slave Error Interrupt Enable 0 (0): MPU Bus Slave Error interrupt is disabled. 1 (1): MPU Bus Slave Error interrupt is enabled. |
| BUSMEN | MPU Bus Master Error Interrupt Enable 0 (0): MPU Bus Master Error interrupt is disabled. 1 (1): MPU Bus Master Error interrupt is enabled. |
| SPEEN | CPU Stack Pointer Monitor Interrupt Enable 0 (0): CPU Stack Pointer Monitor interrupt is disabled. 1 (1): CPU Stack Pointer Monitor interrupt is enabled. |
| Reserved | These bits are read as 000. The write value should be 000. |